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    • Verilog HDL&VHDLテストベンチ記述の初歩 論理回路の検証で用いるHDL文法とノウハウ デザインウェーブムック/安岡貴志【著】

    • Auction ends12/28/2024 18:04 PM (Tokyo)
    • Current Time12/21/2024 18:04 PM (Tokyo)
    • Bids0
    • Availability 1 pcs
    • Leading Bidder
    • VAT Tax: 10 %
    • Return Policy: Not possible
    • Item condition: USED20
    • Shipping in Japan: Not Free
    • Auction ID: x1155658619
    • Automatic Extensionfalse
    • Item location: 神奈川県
    • Seller items: bookoff2022_1st All seller's items
    • Seller's Rating: 130912

    • Current Price

      ¥1,650 (~$10)

      (¥1,815 including tax)

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    • Buyout Price

      ¥1,650 (~$10)

      (¥1,815 including tax)

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