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    • ＨＤＬによるＶＬＳＩ設計 ＶｅｒｉｌｏｇＨＤＬとＶＨＤＬによるＣＰＵ設計／深山正幸(著者),北川章夫(著者),秋田純一(著者),鈴木正国(著

    • Auction ends10/03/2024 22:30 PM (Tokyo)
    • Current Time09/27/2024 02:53 AM (Tokyo)
    • Bids0
    • Availability 1 pcs
    • Leading Bidder
    • VAT Tax: 10 %
    • Return Policy: Not possible
    • Item condition: USED20
    • Shipping in Japan: Not Free
    • Auction ID: t1149825869
    • Automatic Extensionfalse
    • Item location: 神奈川県
    • Seller items: bookoff2022_1st All seller's items
    • Seller's Rating: 127313

    • Current Price

      ¥990 (~$6)

      (¥1,089 including tax)

    • Buyout Price

      ¥990 (~$6)

      (¥1,089 including tax)

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